SSRLabs' I/O Coprocessors are parallel accelerators for I/O tasks that can and should be be offloaded off a general-purpose CPU. Due to their high-bandwidth interfaces both to memory and to I/O they scale out in a more linear fashion than any other I/O accelerator. We have equipped the I/O Coprocessor with a number of hardware accelerators for the most common I/O operations. They are accessible via open source application programming interfaces (APIs).
SSRLabs' Floating Point Coprocessors are massively parallel accelerators for traditional HPC such as FEMs, Fourier Transforms and field solvers with an industry-leading performance. Due to their high-bandwidth interfaces to memory and to other coprocessors and the fact that they are not constrained to SIMD operation they scale out in a more linear fashion than any other accelerator.
SSRLabs' very large capacity Memory ASICs are Hybrid Memory Cube (HMC) based memories with all of the advantages of standard HMC memories with the added benefit of substantially higher densities. Since they can be programmed to be volatile or non-volatile, they can be used in storage appliance applications where in-memory compute is a requirement, with or without a file system.
While developing SSRLabs' pScale™ Coprocessors we have created non-core IP and synthesizable building blocks that we are interested in licensing out or selling. These building blocks are related to I/O, memory host adapters (Hybrid Memory Cube) and other components, DSPs, IoT and some image processing and math functions.